A 256 Channel, Self-Calibrating Stimulator SoC in 65 nm With Per-Channel Electrode Shorting Switch

Minimizing the channel area is essential for achieving high resolution in cortical neurostimulators. This is, however, complicated by on one hand the high impedance of microelectrodes, necessitating bulky high-voltage circuits to deal with the resulting high swing, and on the other hand the requirement for accurate charge balancing, often resulting in large analog circuits. To address these challenges, we present a 256 channel neurostimulator SoC which employs transistor stacking in 65 nm standard CMOS to achieve 10.4 V output swing as well as digital time domain calibration (DTDC) for charge-balanced stimulation. Stimulator variability is mapped on a model capturing the process variability in only 34 bytes per channel, allowing on-chip storage and on-the-fly computation of DTDC corrections. Furthermore, a novel HV shorting switch is included in every channel which allows discharging the electrode. The switch withstands an 11 V output swing in both ON and OFF conditions with an average on resistance of 4k$\Omega $. Including both the HV switch and global DTDC overhead, the effective area per channel is only 0.0206 mm2.