A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques

IEEE Transactions on Circuits and Systems I Regular Papers 2026

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Authors: Yi Liu, Zixi Jing, Zhiyu Liu, Wen Yang, Chi C. Yip, Liang Wu, Howard Cam Luong
DOI: 10.1109/tcsi.2026.3660911
Cited by: 0

Abstract

An FMCW frequency synthesizer features fractional bandwidth boosting (FBWB), phase-noise correlation and cancellation, a digitally-controlled oscillator (DCO) with fast look-up table (LUT) initialization scheme, ultra-fast low-power MMD. With a bandwidth-boosting factor of 2.4, the prototype measures a continuous chirp fractional bandwidth (FBW) of 67.2%, frequency tuning range (FTR) of 111%, PN of −121.5dBc/Hz at 1MHz offset from 7.25GHz, jitter of 88 fs, and 0.06ms LUT convergence time while consuming 31.7 mW, corresponding to FOMTof −204.7dB.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design Analog and Mixed-Signal Circuit Design

Publication details

Journal / source
IEEE Transactions on Circuits and Systems I Regular Papers
Volume
73
Issue
5
Pages
3166–3179
Publication date
10 February 2026
Language
EN