A Low Area-Time ECPM Hardware Accelerator Over Curve25519 on FPGA

In this paper, we explore a low area-time elliptic curve point multiplication (ECPM) hardware accelerator over Curve25519. Firstly, we analyze the correlation of the data hazards of LADDER (main operation), the number of pipeline stages in modular multiplication (MM), and the number of iterations of multiplier in MM, and then establish an equation among them. Based on this equation, a new iterative hardware model of modular multiply-accumulator (MMAC) with stage=10 using a 128-bit multiplier, and a new LADDER scheduling are proposed to support high-performance scenarios for Curve25519 ECPM. Secondly, based on the proposed method, we propose a new 255-bit iterative MMAC. Finally, we explore the trade-off between area and time, present an efficient hardware design to accelerate the Curve25519 ECPM. The proposed accelerator is implemented on the Xilinx XC7Z020 platform. The results show that the proposed accelerator costs 2,367 Slices and 36 DSP blocks, with a clock frequency of 298 MHz. When calculating one Curve25519 ECPM, compared to previous designs with the best area*time (AT) value, the AT value of this design is 220% superior to their design, while the area and time have improved by 52% and 108% compared to theirs, respectively.