D6CIM: 60.4-TOPS/W All-Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8 b Fixed-Point Arithmetic in a 28-nm CMOS

This article presents an all-digital 6T-SRAM-based compute-in-memory (D6CIM) macro that supports 1-to-8-bit fixed-point vector matrix multiplication. The D6CIM is fully digital, employing only digital standard cells and 6T SRAM bitcells. The D6CIM adopts a time-sharing architecture with an optimal degree of time-sharing to maximize the product of compute density and weight density. It also features several circuit techniques, namely non-precharge single-ended access, hybrid compressor adder-tree circuits, and bidirectional shift-accumulation. We prototype the D6CIM macro in a 28-nm CMOS technology. The maximum operating frequency is ~360 MHz in a 1.1-V supply. The energy efficiency is measured at up to 60.4 TOPS/W. It achieves a compute density of 1.46 TOPS/mm2and a weight density of 1005 kb/mm2. Compared to prior state-of-the-art CIM macros, the D6CIM achieves 1.3-4.8X improvement in the product of energy efficiency, compute density, and weight density.