Decision-Window Load Modulation for Noise Reduction in Column-Parallel SS-ADC-Based CMOS Image Sensors

We address a long-standing conflict in SS-ADC-based CMOS image sensors (CIS): correlated-double-sampling (CDS) accuracy favors high OTA gain and wide bandwidth, whereas low decision noise during A/D conversion benefits from a much narrower effective noise bandwidth (ENBW). We propose decision-window load modulation (DWLM), a column-level technique that adds a small load modulation capacitive load to the comparator output and enables it only within the predicted decision window. This time-localized pole shift preserves CDS fidelity while shrinking the in-band noise integral during the conversion instant. We develop a unified noise analysis with DWLM, derive closed-form ENBW reductions, and provide sizing rules for the load modulation capacitive load under delay constraints and redundancy. Compared with oversampling/multi-sampling approaches, DWLM achieves measurable TN reduction without extra cycles, and remains compatible with Correlated Multiple Sampling (CMS) for additional averaging. A$640\times 480$prototype fabricated in 180-nm CMOS integrates column-parallel 10-bit SS-ADCs with dual-stage DWLM. Under dark conditions, the proposed scheme lowers temporal noise by 27.21% at$\times 1$gain and 20.04% at$\times 16$gain. The proposed design achieves competitive figures of merit:$1.811~\text {mV}_{\text {rms}}\cdot \text {nJ/pixels}$, and$1.768~\text {mV}_{\text {rms}}\cdot \text {pJ/(pixels} \cdot \text {lsb)}$, indicating the superior performance compared to state-of-the-art designs.