A 91.4-dB SNDR 2-MS/s 18-bit SAR ADC With Enhanced Optimal-Combination-Algorithm-Based Calibration
Abstract
This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOMS,SNDR(including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors’ knowledge, this is the first high-precision (resolution$\geq 16$bit) data converter adopting OCA-based calibration.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
CCD and CMOS Imaging Sensors
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- IEEE Transactions on Circuits and Systems I Regular Papers
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 73
- Issue
- 8
- Pages
- 5154–5167
- Publication date
- 3 April 2026
- Language
- EN