A 13-bit 70-MS/s SAR-Assisted Cyclic ADC With Charge-Reused 2-bit/Cycle Operation
Abstract
This article presents an energy-efficient 13-bit high-speed SAR-assisted cyclic ADC. The$1^{\text {st}}$stage 6-bit SAR ADC coarsely quantizes the input signal. The proposed charge-reused 2-bit/cycle cyclic ADC doubles the conversion speed with 50% reduction in capacitor number. Owing to the comparator noise suppression circuit and mismatch robustness of the cyclic ADC, an interstage gain of only$2\times $is required, which significantly relaxes the amplifier design and improves its total harmonic distortion (THD). Fabricated in 40nm 1P8M CMOS, the proposed SAR-assisted cyclic ADC achieves 13b resolution with SNDR and SFDR of 66.5dB and 80.1dB, respectively, with a Nyquist-rate input at 70MS/s without calibration while consuming 0.88mW power, yielding FoMSand FoMWof 175dB and 6.9fJ/conv., respectively. The ADC demonstrates a sub-1dB SNDR variation across the measured 9 chips, presenting the robustness against variations.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
CCD and CMOS Imaging Sensors
Low-power high-performance VLSI design
Publication details
- Journal / source
- IEEE Transactions on Circuits and Systems I Regular Papers
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 73
- Issue
- 8
- Pages
- 5142–5153
- Publication date
- 12 May 2026
- Language
- 영어