A 3.2-mW Quad-Core CMOS Class-C VCO Achieving 197.1-dBc/Hz Peak FoM at 0.7-V Supply

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Authors: Sheng Wang, Chao Yang, Jianjun Zhou, Jing Jin
Cited by: 0
References: 18

Abstract

This brief presents a low-power quad-core complementary MOS (CMOS) class-C oscillator utilizing a triple-coupled transformer resonator. The proposed transformer establishes coupling between the gate and drain nodes, thereby decoupling the bias voltage of the transistor pairs. Benefiting from the high current efficiency of the CMOS class-C topology combined with the multi-core coupling technique, the proposed oscillator achieves low power consumption and low phase noise (PN). Additionally, a startup detection circuit is further incorporated to confirm the startup condition over process. The proposed VCO is fabricated in a 40 nm CMOS process, consuming 3.2 mW from a 0.7 V supply. The PN at 1 MHz offset is -128.5 dBc/Hz from a 10 GHz carrier (after on-chip divider-by-2), resulting in a figure of merit (FoM) of 197.1 dBc/Hz.

Fields of Study & Subjects

Radio Frequency Integrated Circuit Design Advanced Power Amplifier Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
IEEE Transactions on Circuits & Systems II Express Briefs
Volume
73
Issue
3
Pages
238–242
Publication date
5 January 2026