Efficient Asynchronous Sampling of Ripple Counter in VCO-ADC Using Ripple Register and Event Arbitration
Abstract
We present a power and area-efficient solution for robust asynchronous sampling of a ripple counter for coarse-fine VCO-ADCs. We show that by replacing the parallel register with a delay-matched sequential register and utilizing asynchronous arbitration, sampling errors are avoided. Post-layout simulation of a 7-bit system shows that our proposed solution tolerates VCO frequencies 197× higher than the baseline design, while requiring a 42% increase in power and a 26% area overhead, thereby improving upon a state-of-the-art double-counter solution.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- IEEE Transactions on Circuits & Systems II Express Briefs
- Volume
- 73
- Issue
- 2
- Pages
- 138–142
- Publication date
- 12 January 2026