A 0.018-mm 2 0.05–2 GHz Balun-LNA With Post-Linearization and Balanced Loads Achieving 33.5-dBm OIP3 and 3.7-dB NF

In this article, a 0.05–2 GHz broadband balun-low-noise amplifier (LNA) achieving high linearity and balanced output loading using a post-linearization current-bleeding (CBLD) technique is presented. The proposed architecture is based on a conventional common-gate (CG) and common-source (CS) balun-LNA topology, in which the CBLD path simultaneously provides symmetric loads and performs post-distortion (PD) linearization without any auxiliary stage or additional current consumption. This dual-function implementation enables significant third-order linearity improvement over a wide frequency range while maintaining low noise and stable input matching. Fabricated in a 28-nm CMOS process, the proposed balun-LNA achieves a noise figure of 3.7–4.1 dB, a maximum voltage gain of 20 dB, and an input return loss (S₁₁) better than −10 dB across a 3-dB bandwidth of 2 GHz. The measured IIP3 ranges from 9.8 dBm to 13.5 dBm, corresponding to a peak OIP3 of 33.5 dBm. The LNA consumes 10.2 mA from a 1.2-V supply and occupies an active area of only 0.018 mm².