A 37–48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique

This brief presents a 37–48 GHz push-push doubler (PPD) exhibiting excellent harmonic rejection. To address the challenge of wideband fundamental suppression in millimeter-wave PPDs, a staggered fundamental suppression technique is proposed, which integrates a frequency-selective degeneration network with an asymmetric-capacitor-loaded balun. In addition, a split-capacitor-based harmonic nulling scheme is employed to suppress the 4th harmonic. The proposed PPD is fabricated in a 40 nm CMOS process, and measurement results reveal a fundamental rejection ratio (FRR) exceeding 47.8 dBc, a maximum 4th harmonic rejection ratio (HRR) of 46.9 dBc, a peak conversion gain of –0.5 dB, and a peak drain efficiency of 25.1%. Compared to a reference PPD, the proposed PPD exhibits over 12 dB FRR enhancement across the entire bandwidth, demonstrating the effectiveness of the proposed staggered fundamental suppression technique