A 1-kHz BW 106-dB SNDR DT Zoom ADC

This paper presents a high-linearity discrete-time (DT) Zoom analog-to-digital converter (ADC). To enhance linearity and simplify implementation, a coarse first-order sigma-delta modulator (SDM) followed by a 16-tap finite-impulse-response (FIR) DAC is employed, inherently suppressing harmonic distortion and eliminating the complex hardware associated with a conventional successive-approximation register (SAR) ADC and dynamic element matching (DWA). The proposed architecture achieves a 35 dB improvement in third-harmonic distortion (HD3) over a conventional 4-bit SAR-based implementation. Fabricated in a 180-nm CMOS process, the prototype measures a 106-dB signal-to-noise-and-distortion ratio (SNDR), a 109.7-dB dynamic range (DR), and a 111.1-dB spurious-free dynamic range (SFDR) over a 1-kHz bandwidth, while consuming 63.1 μW from a 1.8-V supply at an 800-kHz sampling rate. This corresponds to a Schreier figure-of-merit (FoM) of 178 dB based on SNDR and 181.7 dB based on DR, without employing DWA techniques.