A Compact 2–19.5-GHz 150-ps True Time Delay Circuit With High Area Efficiency of 882.4-ps/mm 2

In this paper, a novel switched true-time-delay (TTD) circuit is presented using a 65-nm CMOS process. It employs cascaded series‑capacitor all‑pass networks (SCAPNs) for delay compensation, along with a novel layout based on an 8‑shaped transformer, to construct a compact and broadband delay unit. The design leverages the self-canceling coupling property of an 8-shaped transformer to integrate the inductors required for both APN stages into a single component, achieving an ultra-compact footprint. To verify the proposed structure, a 5- bit switched-line TTD is constructed using two single-pole double-throw (SPDT) and four double-pole double-throw (DPDT) switches. Experimental results show that, with a core size of only 0.209 × 0.816 mm², the proposed TTD circuit achieves a maximum delay tuning range of 150 ps and a minimum delay step of 4.838 ps from 2 to 19.5 GHz, while maintaining RMS delay error below 3.7 ps. The corresponding area efficiency of 882.4 ps/mm² represents a record high for switched-line TTDs.