Sliding-Block DFE Error Propagation Correction Under Uncertainty With Reverse-Decision Evaluation for High-Speed Wireline Receiver on FPGA

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Authors: Se-Ung Park, Junyeong Lee, Jaemin Choi, Jung‐Hoon Chun
Cited by: 1
References: 12

Abstract

This brief presents a PAM-4 sliding-block decision feedback equalizer (SB-DFE) employing the correction under uncertainty with reverse-decision evaluation (CURE) scheme. Conventional SB-DFE resolves timing bottlenecks in high-tap DFE by breaking the feedback loop, but remains vulnerable to intra-block error propagation. To address this, the CURE scheme is integrated for localized sequence estimation, which conditionally evaluates candidate sequences prompted by unreliable decisions to suppress error propagation with minimal complexity. Leveraging the SB-DFE structure to compensate for long-tail post-cursor intersymbol interference enables the use of a shortened feed-forward equalizer (FFE). This provides a higher signal-to-noise ratio for CURE than 4-state maximum likelihood sequence detection (MLSD), as the latter suffers from noise amplification in its longer FFE. Field-programmable gate array-based link emulation confirms the proposed architecture outperforms 4-state MLSD across various noise conditions. ASIC synthesis in a 28-nm FD-SOI technology further confirms that the design reduces area and power by 2.90× and 4.05×, respectively, relative to the MLSD benchmark.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Low-power high-performance VLSI design Digital Filter Design and Implementation

Publication details

Journal / source
IEEE Transactions on Circuits & Systems II Express Briefs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
73
Issue
5
Pages
563–567
Publication date
31 March 2026