Impact of Device Geometry Variations on DC and Analog/RF Performance of Advanced Nanosheet FETs with Si 3 N 4 Spacer Dielectric

This work presents a comprehensive comparative analysis of use of spacer dielectric (Si3N4) on DC and Analog/RF performance metrics of three advanced nanosheet architectures: the stacked nanosheet field effect transistor (SNSFET), Tree structured field effect transistor (TreeFET), and TreeFET with H-shaped channels (HS TreeFET). As device scaling nears its physical constraints, novel multi-bridge-channel FET provides superior electrostatics and higher drive performance. The TreeFET architecture presents a branched channel topology that enhances gate control and carrier transport. The integration of H-shaped channels in TreeFET enhances effective channel width while preserving a compact footprint and short-channel immunity. Extensive device simulations are performed utilizing sophisticated TCAD tools to assess threshold voltage (Vth), subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON current, ION/IOFFratio, transconductance (gm), cut-off frequency (fT), gain bandwidth product (GBP), and transconductance frequency product (TFP). Results demonstrate that HS TreeFET provides higher DC and Analog/RF performance due to an H-shaped channel and superior gate control. TreeFET exhibit superior electrostatic integrity compared to traditional NSFET, while preserving competitive RF attributes. The HS TreeFET based CMOS inverter has better noise margin compared to TreeFET and SNSFET. This study emphasizes the design compromises and performance advantages of novel nanosheet designs, providing significant insights for forthcoming CMOS technology nodes aimed at high-performance logic and RF system-on-chip (SoC) applications.