SiC MOSFET Gate-Oxide and SiC/SiO 2 Interface Defect Charge Movement Based on the Hi-Lo C ISS - V G Method Under HTGB Stress

The high and low frequency (Hi-Lo) CISS-VG method is carried out to analyze defect charge movement at the gate-oxide interface. The method distinguishes the impact of fast and slow traps on SiC MOSFET capacitors. Furthermore, the initial defect distribution and defect charge movement trend under positive bias temperature instability (PBTI) conditions are predicted. The commercial 1.2 kV SiC MOSFETs are analyzed during 450-hour high temperature gate bias (HTGB) stress and 450-hour high temperature stress (HTS). The lowest points of the high frequency 1 MHz CISS curves in both HTGB and HTS show a significant downward shift at both 300-hour and 450-hour, from 1579 pF to 1425 pF. This indicates the hole charge accumulation of deep-level donor-type traps under long-term BTI conditions, as validated by the theoretical analysis and TCAD simulations.