Impact of EP-CG Interlayer Dielectric on Performance of L-Shaped Split-Gate Flash Memory

Split-gate L-shaped floating-gate flash cells in 55 nm are reported that reach a 5.6 V window, 10. P/E cycles, and a tight V. distribution for both SLC (Single-Level Cell) and TLC (Tri-Level Cell), while cutting two critical masks. The advance is enabled by a 27 nm triple-oxide (Dry/HTO/Dry) inter-layer dielectric that raises control-gate-to-erase-poly breakdown voltage to 18 V. The sharpening of the floating-gate tip, together with the L-shaped floating gate, suppresses the EP-to-FG coupling ratio (ECR) to 0.05 while keeping the CG-to-FG coupling ratio (GCR) at 0.64, delivering low-voltage erase performance while maintaining well-controlled floating gate control.