On the Reliability of Complementary Field Effect Transistor: Unveiling the Role of Grain Granularities and Random Fluctuations

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Authors: Sandeep Kumar, Deven H Patil, Sunil Rathore, Ankit Dixit, Naveen Kumar, Vihar Georgiev, S. Dasgupta, Navjeet Bagga
Cited by: 0
References: 33

Abstract

This study presents a comprehensive statistical reliability analysis of monolithic Complementary Field Effect Transistors (CFETs), focusing on the impact of process-induced variations. The analysis highlights key sources of variability, including Metal Gate Granularity (MGG), Poly Grain Granularity (PGG), Random Dopant Fluctuation (RDF), and Line Edge Roughness (LER). In smaller geometries, the gate metal (or poly-gate) grain granularities play a significant role in threshold voltage (Vth) variations, raising severe reliability concerns. Through calibrated statistical TCAD simulations, the ON current (ION) variation of 2.82 μA (2.85 μA) is observed in the nFET (pFET) side of CFET, due to MGG for experimentally reported 5 nm grain size. In advanced technologies like high bandwidth memory (HBM), the gate is made of polysilicon that suffers from the PGG in sub-3 nm node devices. The observed coefficient-of-variance (CV) of pFET (2.19) is higher than nFET (1.45), which shows higher variability in pFET due to poly grain size variations. Further, the process-induced RDF and LER significantly alter the Vth. Random numbers are generated by doping atoms in the Voronoi volume of each vertex to quantify the undoped and doped channels to statistically analyze the RDF. In contrast to a doped channel with σVthof 9 mV (7 mV) for nFET (pFET), the undoped scenario yields a default standard deviation (σVth) of 2 mV. To characterize LER, correlation length (Λ) is a prime factor; as Λ approaches the sheet width, CV increases by 24.32% (37.22%) in nFET (pFET). Thus, the results underscore the need for stringent control over grain morphology, doping precision, and edge definition to ensure reliable CFET performance.

Fields of Study & Subjects

Advancements in Semiconductor Devices and Circuit Design Low-power high-performance VLSI design Semiconductor materials and devices

Publication details

Journal / source
IEEE Transactions on Device and Materials Reliability
Volume
26
Issue
1
Pages
365–371
Publication date
16 February 2026
Language
EN