Mitigating the Process Variations in Negative Capacitance Junctionless Device and Circuit

Through well-calibrated simulations, this work presents a comprehensive analysis of process-induced variations in on-current (ION), off-current (IOFF), and threshold voltage (Vth) for negative capacitance (NC) junctionless (JL) transistors designed on bulk substrate. The performance and variability metrics are benchmarked against SOI-based NCJL transistors. The results reveal a significant reduction in (ION), (IOFF), and (Vth) due to the variation in geometrical device parameters in bulk NCJL devices. The outperformance is primarily due to the shift in the conduction channel towards the front surface, which enhances the effectiveness of the negative capacitance effect in bulk NCJL device. In addition, the lower variability observed in bulk NCJL devices translates into improved noise margin (NM) and reduced process-inducedNMfluctuations in inverter circuits. Results reported for the first time demonstrate the enhanced device- and circuit-level performance of bulk NCJL transistors in comparison to their SOI counterparts.