Enhancement-Mode Operation and Stability Improvement in Ultrathin ALD-InO$_{\textit{x}}$ FETs With AlO$_{\textit{x}}$ /HfO$_{\textit{x}}$ Gate Dielectric

The improvement in electrical properties of bottom-gate AlO$_{\textit{x}}$-passivated 1.8-nm-thick InO$_{\textit{x}}$FETs by inserting a 1.1-nm thick AlO$_{\textit{x}}$interlayer between the oxide channel and HfO$_{\textit{x}}$dielectric is experimentally investigated. The ultrathin AlO$_{\textit{x}}$interlayer prevents impurities diffusion from the HfO$_{\textit{x}}$layer into InO$_{\textit{x}}$channels during fabrication, which can address the negative initial${V}_{\text {th}}$issue in devices with single-HfO$_{\textit{x}}$dielectric. The InO$_{\textit{x}}$FETs with AlO$_{\textit{x}}$/HfO$_{\textit{x}}$dielectric provide a positive threshold voltage (${V}_{\text {th}}\text {)}$of 0.22V and the subthreshold swing (SS) of 65.8 mV/dec after annealing in N2ambient at$300~^{\circ }$C. Due to the reduction of interface trap density and the number of fixed charges by an ultrathin AlO$_{\textit{x}}$interlayer, devices with$300~^{\boldsymbol {\circ }}$C annealing show excellent positive and negative bias instability of 52 and 58 mV for 3-h stressing at a${V}_{\text {g}}-{V}_{\text {th}}$of$\boldsymbol {\vert }{{1}}{\,}\text{V} \boldsymbol {\vert }$, respectively. Finally, the possible mechanisms of bias stress instability in InO$_{\textit{x}}$FETs with AlO$_{\textit{x}}$/HfO$_{\textit{x}}$dielectric are discussed.