Hardware Emulation of Membrane Potential Using a 1T1C FeFET–Capacitor Structure for Neuromorphic Applications

With the increasing demand for high-density implementation and low-power operation of artificial intelligence (AI), inherent limitations of the conventional von Neumann architecture have been recognized, highlighting the development of energy-efficient synaptic devices as a critical issue in neuromorphic systems. In this study, a novel synaptic architecture was proposed based on a 1T1C structure, in which a ferroelectric field-effect transistor (FeFET) is connected in series with a capacitor, to realize analog responses similar to the membrane potential of biological neurons through circuit-level integration based on the 1T1C synaptic behavior. The transfer characteristics of the FeFET were experimentally measured and modeled, and circuit simulations emulating neural network structures reproduced dynamic membrane potential (${V} _{\text {mem}}\text {)}$variations using 196 cells (input-to-hidden layer) and 80 cells (hidden-to-output layer). Through evolutionary symbolic regression, a mathematical model expressing${\Delta }$Vmemas a function of${\Sigma } {G}$and the preceding${V} _{\text {mem}}$was derived, and its implementation in a spiking neural network (SNN) achieved 95.5% recognition accuracy for MNIST image classification. The energy consumption of the synaptic circuit was further estimated to be 239 nJ/inference, and scaling the device dimensions down to the 100-nm regime suggested a reduction to 3.74 pJ/inference. These findings demonstrate the extremely high potential of the proposed approach for ultralow-power operation, indicating that the FeFET–capacitor 1T1C structure constitutes a promising synaptic device architecture for high-density neuromorphic systems and edge AI applications.