Investigation of Hot Carrier Injection During GIDL Erase Operation in 3-D NAND Flash Memory

The physical mechanism and transient behavior of hot carrier injection (HCI) during the gate-induced drain leakage (GIDL) erase operation in 3-Dnandflash memory devices are systematically investigated based on both experimental and simulation data. The transient analysis of HCI focuses on the evolution of two key physical parameters: the potential difference between the source line/bitline (SL/BL) and the string, and the maximum lateral electric field in the select gate transistor (SG) channel. It is found that a slow rise of the string potential, resulting from the accumulation of GIDL-generated holes in the floating string, induces significant HCI at SG. The dependence of HCI on critical design parameters, including the number of wordline (WL) layers, SL/BL voltage rise time, offset length, SG gate bias, and its rise time, is also analyzed, revealing a strong correlation between HCI behavior and GIDL efficiency. The presented systematic analysis provides physical insight and design guidelines for mitigating HCI-induced SG degradation, thereby enhancing the reliability of state-of-the-art 3-Dnandflash memory technologies.