High- κ Capping Layer Effects on Carrier Polarity and Reliability of SWNT Field Effect Transistors With Spin-on-Glass Buffer Layer

The electrical performance and reliability of spin-on-glass (SOG)/high-$\kappa $single-walled carbon-nanotube (SWNT) field-effect transistors (FETs) were examined through the dual-gate operation, pulsed-bias measurements, and low-frequency-noise (LFN) analyses. Hysteresis and bias-stress instabilities are governed by interface-trap dynamics, where Al2O3forms shallow fast traps, HfO2exhibits the moderate activity, and ZrO2introduces deep slow traps affecting long-term stability. Devices with HfO2capping showed minimal hysteresis (~0.1 V), while ZrO2-based transistors achieved the highest field-effect mobility (~35 cm${}^{{2}}~ \cdot $V${}^{-{1}}~\cdot $s${}^{-{1}}\text {)}$and the lowest contact resistance. Under ±3-V gate stress, electron trapping dominated ($\Delta {V}_{\text {TH}} \approx ~0.6$–0.9 V), whereas the hole trapping was effectively suppressed dues to large injection barriers ($\approx$2.5–3.4 eV). The noise spectra followed the carrier-number-fluctuation (CNF) model, confirming the trap-density order Al2O${}_{{3}} \gt $HfO${}_{{2}} \gt $ZrO2. All fabrication steps were performed below$250~^{\circ }$C, ensuring compatibility with monolithic 3-D (M3D) and system-in-package (SiP) platforms for reliable, low-power SWNT electronics targeting sub-3-nm nodes.