A Novel Read Disturbance-Free AND-Type Backside Ferroelectric Field-Effect Transistor (BF-FET) Array for Read-Intensive Artificial Intelligence

We propose a novel and-type memory array featuring a backside ferroelectric field-effect transistor (BF-FET). This architecture places the ferroelectric layer on the backside of a thin polysilicon channel. A key novelty lies in connecting all ferroelectric layers to a common back gate (BG), which eliminates the need for an additional word line (W/L) to control the BG bias, thereby substantially reducing design complexity. Furthermore, the BF-FET exhibits inherent immunity to read disturbance originating from the minor loop of ferroelectric materials, as its polarization switching is completely decoupled from the read operation. The BF-FET demonstrates a three times larger memory window than Fe-FETs with the same thickness of the ferroelectric and channel layers, enabling robust multilevel cell (MLC) operation. The convolutional neural network (CNN) simulation demonstrates that the BF-FET-based synaptic array exhibits superior endurance, with its recognition rate remaining above 95% even after 10(7) repeated read cycles.