An Improved Nanosheet Compact Model Capturing Spacer and Epitaxial Geometry Effects for RF Applications

Accurate modeling of geometry-dependent parasitics is essential for reliable RF performance prediction in nanosheet field-effect transistors (NSFETs). In this work, we investigate the influence of spacer thickness$\text {(}{L}_{\text {sp}}\text {)}$and source/drain epitaxial height$\text {(}\textit {H$\,$}\text {sde}\text {)}$on current, capacitance, and transconductance$\text {(}{g}_{m}\text {)}$behavior of NSFETs designed for 3-nm technology nodes. Physical analysis reveals that reducing${L}_{\text {sp}}$lowers series resistance but increases parasitic capacitance$\text {(}{C}_{\text {par}}\text {)}$and degrades RF figures of merit, whereas reducing$\textit {H$\,$}\text {sde}$alleviates${C}_{\text {par}}$and improves${g}_{m}$by lowering source/drain resistance. Guided by these physical insights, we develop empirical yet geometry-scalable compact models within the BSIM-CMG framework that explicitly incorporate${L}_{\text {sp}}$and$\textit {H$\,$}\text {sde}$dependencies. The proposed model shows excellent agreement with 3-D TCAD simulations, accurately reproducesI–VandC–Vcharacteristics across varying geometries, and successfully passes RF benchmark tests, including cutoff frequency$\text {(}{f}_{T}\text {)}$and harmonic balance (HB) analysis. This work highlights the critical role of geometry-driven parasitics in NSFET design and provides a compact modeling solution that is robust, accurate, and ready for integration into advanced RF circuit design flows.