Mitigating Charge Injection Bottlenecks via Dual-Doped Source/Drain for High-Speed Low-Voltage Capacitorless Dynamic Memory
Abstract
This work demonstrates the feasibility of thermionic injection-based program and erase operations for enabling a low-voltage, high-speed capacitorless dynamic random access memory (DRAM) via a dual-doped (DD) source/drain (S/D) transistor. The proposed capacitorless DRAM achieves a low latency ($85~^{\circ }$C) at a logic-compatible supply voltage of ±0.6 V while maintaining functionality at elevated temperatures (~5 ms at$125~^{\circ }$C). Results highlight the usefulness of DD-S/D engineering for high-speed, energy-efficient embedded cache and edge computing.
Fields of Study & Subjects
Advancements in Semiconductor Devices and Circuit Design
Semiconductor materials and devices
Low-power high-performance VLSI design
Publication details
- Journal / source
- IEEE Transactions on Electron Devices
- Volume
- 73
- Issue
- 4
- Pages
- 1911–1917
- Publication date
- 24 February 2026
- Language
- EN