Drastic Hysteresis Reduction and Intrinsic Carrier Switching in MoS 2 Transport Using Polymer-Capped Gate Dielectrics

Unintended excess channel carrier density and hysteresis in charge transport in 2-D transistors are a serious reliability challenge in large area commercial 2-D logic devices. Currently used bulk gate dielectrics such as SiO${}_{x}$, Al2O3, HfO2have un-passivated interface imperfections, majorly contributing to hysteresis, threshold voltage shifts and mobility degradations. Here, we show using targeted experiments and interface conductivity models that a polyimide (PI) gate dielectric drastically reduces the surface trap site density by three orders, making hysteresis barely visible in transport characteristics. Strongly electronegative species in the molecule drastically reduces growth induced electron density switching the as-grown n-type material to a p-type semiconductor. Detailed investigations show the crucial role of surface chemistry and the subtle role of the polymer cap in improving the mobility, sub-threshold slope, and the ON-OFF ratio of the MoS2transistor in comparison with the SiO2dielectric used here as a control sample.