Engineering Cryogenic FETs: Addressing SCEs and Impact of Interface Traps Down to 2-K Temperature

This article presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from${T} =2$to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at${T} =2$K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when theon-state bias is adjusted to account for the trap-induced${V}_{t}$shift, interface traps are found toworsen${I}_{\textsc{on}}/{I}_{\textsc{off}}$along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation$\sigma $of the trap distribution modulates these behaviors: highly localized traps ($\sigma \sim {1}$–2 nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions ($\sigma \ge {50}$nm) elevate the entire barrier and suppress SCEs until saturation as$\sigma \to {L}_{g}$. The TCAD predictions closely match experimental data at 4.2, 77, and 300 K, providing design guidelines to optimize${I}_{\textsc{on}}/{I}_{\textsc{off}}$, SS, mobility, and DIBL for cryogenic CMOS technology nodes.