Bias-Polarity-Dependent Electrical Characteristics of 1x nm DRAM Capacitors for Robust Cryogenic Memory Applications

This study explores the electrical behavior of capacitors with symmetric trilayer dielectrics in 1x nm dynamic random access memories (DRAMs) for cryogenic computing. Depositing a lower dielectric layer on top of the bottom electrode (BE) triggers oxygen vacancy defect generation via a chemical reaction. Electrical measurements over a wide temperature range (370–77 K) elucidated the impact of these defects on the conduction. Applying a positive voltage to the top electrode (TE) induces more charges due to electrons trapped near the BE, leading to a faster capacitance increase. The bias-polarity-dependent transport properties of the trilayer exhibit trap-assisted tunneling (TAT) in the low-voltage regime, transitioning to Poole–Frenkel (PF) emission, and ultimately Fowler–Nordheim (FN) tunneling in the high-voltage regime. We observed weakening of abundant traps near the BE interfacial barrier, allowing PF conduction to dominate over TAT. Under constant voltage stress (CVS), the substantial accumulation of trapped electrons near the BE interface accelerates toward the opposite plate because of the electric field. This resulted in increased current due to defect generation near the TE, thereby making the capacitor vulnerable to stress. Overall, the data retention of DRAM is expected to improve because of the lower current at 77 K. However, careful design of the BE interface is critical for leakage current and stress susceptibility.