Asymmetrical Source/Drain Induced Localized Hot-Carrier Degradation and Parasitic PBTI in n-Type Vertical Nanosheet FET

In this work, the significant impact of asymmetric source/drain parasitic resistance on hot-carrier degradation (HCD) in n-type vertical nanosheet field-effect transistor (VNSFET) is systematically investigated. The parasitic source and drain resistances are extracted using the channel resistance method (CRM) and the constant current method, showing a bottom-to-top resistance ratio of approximately 3:1. Under the normal-mode (with the top terminal as the drain), HCD exhibits a power-law degradation trend, in contrast to the obvious saturation behavior under the reverse mode (with the bottom terminal as the drain). TCAD simulations demonstrate that such resistance asymmetry redistributes the internal voltages: a high lateral field causes channel hot-carrier (CHC) degradation in normal-mode, while the voltage drops across the large top resistance in reverse mode induces a parasitic positive bias temperature instability (PBTI) by the vertical electrical field. This work clarifies the role of parasitic resistance in determining the dominant degradation mechanism in inevitably asymmetric 3-D device architectures, providing key insights into reliability-aware optimization for vertical transistors in next-generation high-density memory and computing systems.