Analysis of Thermal Disturbance in Vertically Stacked Phase-Change Memory Using Multiphysics Simulation

Vertically stacked phase-change memory (PCM) architectures represent a promising strategy for realizing high device density; however, they remain susceptible to thermal disturbance (TD), manifested as heat-induced crosstalk between neighboring cells during switching operations. In this study, thermal effects in 3-D PCM arrays are systematically investigated using a multiphysics simulation framework, where our electrothermal and phase-field models are implemented within a commercial finite element solver. By quantitatively analyzing the effects of intercell spacing and cell dimensions, we identify geometrical regimes where TD can be suppressed without sacrificing memory density. Furthermore, we demonstrate that engineering the cell architecture to enhance thermal boundary resistance (TBR), for example, by incorporating recessed heater structures, significantly mitigates heat transfer to adjacent cells and enables lower reset energy operation. Simulation results further reveal the tradeoffs among heater thickness, interlayer dielectric (ILD) thickness, and device endurance over repeated programming cycles. These insights guide the design of stackable PCM cells for robust, energy-efficient, and scalable memory integration.