Temperature-Dependent Gate Oxide Degradation and Interface-Trap Mechanisms in Planar SiC MOSFETs Under Dynamic Gate Stress

The reliability of the gate oxide in SiC MOSFETs remains a critical concern for high-temperature and high-power applications. Aiming to clarify the temperature-dependent mechanisms of oxide degradation after dynamic gate stress (DGS), this work investigated the gate oxide reliability of four kinds of planar-type SiC MOSFETs under DGS at$25~^{\boldsymbol {\circ }}$C,$75~^{\boldsymbol {\circ }}$C,$125~^{\boldsymbol {\circ }}$C, and$175~^{\boldsymbol {\circ }}$C. The degradation was first characterized by${V} _{\text {th}}$drift, subthreshold swing (SS), subthreshold hysteresis ($\boldsymbol {\Delta } {V} _{\text {th, {sub}}}\text {)}$, and${C} _{\text {iss}}$–${V} _{\text {GS}}$measurements. All devices exhibited${V} _{\text {th}}$drift, either positive or negative, with diverse temperature dependencies: weak correlation (DUT-A), positive correlation (DUT-B), a transition from negative to positive drift with increasing temperature (DUT-C), and aggravated negative drift (DUT-D). Based on trap analysis and technology computer-aided design (TCAD) modeling, a temperature-dependent trap competition (TDTC) mechanism was identified, further revealing that both electron traps near the valence band edge and hole traps near the conduction band edge were induced by DGS. Different formation activation energies and interface qualities caused distinct temperature acceleration effects, leading to different drift directions and diverse temperature dependencies of the devices under tests (DUTs). The above findings enhance the understanding of the temperature-dependent gate oxide degradation under DGS, providing insights into SiC MOSFET reliability.