3-D MOSFET Designs With Deep P Source-Connected JFET for Improved R on

This article presents the design and optimization of 750-V-rated double-trench (DT) MOSFET structures incorporating a deep JFET region in the third dimension and investigates modified unit-cell configurations to assess the tradeoff between Ronreduction and device protection. The single active trench (1-AT) design provides strong device protection but is limited by high Ron, whereas the double active trench (2-AT) design achieves lower Ronat the expense of reduced short-circuit (SC) robustness. Based on this analysis, the proposed split-gate (SG) design increases the channel density and improves the device protection, achieving a 17.5% reduction in Ron(37.5 m$\Omega $) compared to the benchmark DT- MOSFET with an SC withstand time (SCWT) of$6~\mu $s and EF${}_{\text {GOX}} \lt 3$MV/cm. Under matched EFGOXconditions with the DT- MOSFET, the SG design increases the SCWT by$3~\mu $s and improves the Ron–SCWT tradeoff.