Investigation of Degradation Mechanisms in SiC MOSFETs Under Synergy Negative Gate Voltage Stress and High-Temperature Reverse Bias

This article investigates the degradation mechanism of silicon-carbide (SiC) MOSFETs in high temperature reverse bias (HTRB) tests with${V}_{\text {ds}} =1200$V,${V}_{\text {gs}} =0$V, and${V}_{\text {ds}} =1200$V,${V}_{\text {gs}} = -5$V. The experiments show that HTRB tests under −5 V gate voltage conditions result in more severe degradation of threshold voltage (${V}_{\text {th}}$), gate leakage current (${I}_{\text {gss}}$), output curve, and gate oxide capacitance curve compared to those under 0 V gate voltage conditions. Furthermore, testing under −5 V gate voltage conditions ultimately leads to defects in the gate oxide layer of the JFET region. Combined with TCAD simulation, it is shown that when a gate voltage of −5 V is applied, the gate oxide will be subjected to a stronger electric field, higher collision ionization rate, and higher hole interface defect charge than when a gate voltage of 0 V. Moreover, under the condition of −5 V gate voltage, it will lead to higher hole current density in the channel, causing more hole carriers to be trapped in the gate oxide layer traps and leading to degradation of the gate oxide layer. The experimental and Sentaurus simulation results confirm that the reliability of the gate oxide layer of SiC MOSFET decreases under the condition of${V}_{\text {gs}} = -5$V.