Threshold Voltage Variability Induced by Localized Ferroelectric Phase Distributions in FeFET and Its Mitigation Strategies

Threshold voltage variability is a key concern in ferroelectric field effect transistor (FeFET) technology. In this work, a study spanning experiments, modeling, and SPICE simulations is conducted to evaluate the impact of localized FE/ dielectric (DE) distributions on the threshold voltage (${V}_{\text {TH}}$) of FeFET. The device characterization is performed on the 28-nm FeFET foundry platform. The experimental study on device-to-device (D2D) and cycle-to-cycle (C2C) variations reveals that the FeFET can be an asymmetric device, with the VTHshowing dependence on the direction of current flow, as well as the magnitude of applied drain voltage (${V}_{\text {DS}}$) to the device. The TCAD modeling study reveals that the cause of asymmetry is the spatial localization of DE phases that may occur due to the random nature of the distribution. SPICE simulation for two-FeFET-based ternary content-addressable memory (TCAM) reveals that as few as two devices exhibiting the localization-induced threshold voltage shift can lead to a 64-bit search failure. Various strategies are investigated to minimize the impact of such localized phase distribution-induced threshold voltage shift (LPTS) effect. Notably, the capacitive readout of FeFET and the insertion of a floating metal electrode in the gate-stack improve the robustness.