Low-Noise SPADs With Multiwell Configuration

Reducing dark noise while maintaining high photon detection probability (PDP) is a critical challenge for single-photon avalanche diodes (SPADs) in advanced CMOS technologies, where aggressive scaling exacerbates tunneling and dark carrier generation. In this work, a CMOS-compatible SPAD featuring a multiwell configuration is proposed to balance noise suppression with detection efficiency. By tailoring the p-well (PW) and deep PW (DPW) profiles, the structure effectively reshapes the electric field distribution, thereby suppressing tunneling-induced dark counts while enabling robust avalanche triggering. Systematic simulations and experimental characterizations support the proposed design and the observed performance trends. The optimized device achieves a significant dark count rate (DCR) reduction from over$10^{{4}}$to 450Hz at a 4-V excess bias, while maintaining a peak PDP of 49% at 520nm, indicating a favorable tradeoff between low dark noise and high detection capability for CMOS-compatible single-photon imaging.