A New Scan Based Attack on AES With Plaintext Restriction Countermeasure

The scan Design-for-Testability (DfT) architecture, widely embraced in VLSI design to enhance testability and ensure reliability, inadvertently introduces security vulnerabilities. These vulnerabilities could be exploited by attackers to gain unauthorized access to sensitive or confidential data stored within cryptographic chips. Several countermeasures have been proposed to secure crypto chips against scan-based side-channel attacks. Among these, the Plaintext Restriction (PTR) technique emerges as a notably effective countermeasure for its simplicity and effectiveness in thwarting conventional scan attacks. This study conducts a comprehensive vulnerability assessment of the PTR countermeasure. It is observed that while the PTR countermeasure effectively thwarts conventional scan attacks, leakage issues still persist. To exploit this leakage, a more sophisticated scan attack is proposed, allowing the AES encryption key to be retrieved successfully. The proposed attack specifically targets the AES round key, diverging from the conventional scan attacks that primarily focus on the AES encryption key. Subsequently, this paper presents a new countermeasure aimed at addressing this vulnerability. The proposed countermeasure is able to withstand all the conventional and proposed scan attacks without impacting the testability of the design. Moreover, the proposed countermeasure incurs only a minimal area overhead of 0.76% compared to the existing countermeasures.