Variation Resilient Schemes and Approximation-Free Offset Compensation for Reliable ReRAM-Based DNN Accelerators

Deep Neural Networks (DNNs) have achieved out standing performance in various fields. However, as DNNs continue to grow in size, their performance is hindered by the memory wall problem, where data memory bandwidth becomes a bottleneck. Resistive Random Access Memory (ReRAM)-based DNN accelerators offer promising solutions to this challenge, enhancing data processing efficiency. However, these architectures face reliability issues due to cell immaturity, notably device conductance variation and offset currents in High Resistance State (HRS) cells, which compromise DNN accuracy and processing performance. This paper addresses the reliability issues of the ReRAM-based computing-in-memory (CIM) accelerator. In particular, this paper introduces a novel design methodology of shared-exponent deployment on the accelerator, enhancing variation tolerance through fine-grained quantization. In addition, this paper proposes a variation-resilient data encoding to further improve the robustness in combination with the proposed design and introduces a programming scheme for the offset current compensation. Experimental results conducted on various DNN models and datasets reveal that the proposed techniques outperform existing methods in variation tolerance and significantly improves performance and energy efficiency compared to the conventional baseline, even under high variation environments.