An Efficient Ternary in-Memory Computing Architecture With Application in Phonocardiogram-Based Driver Stress Detection
Abstract
Traffic accidents remain a leading global cause of injury and fatalities, with driver stress identified as a significant contributing factor. Traditional stress detection methods, such as ECG-based systems, suffer from bulky designs and limited battery life, restricting their practicality for real-time wearable applications. To address these limitations, this paper presents a novel ternary in-memory computing (IMC) architecture for efficient PCG-based stress classification in power-constrained wearable devices. The proposed design introduces ternary full adder and multiplier circuits based on emerging technologies, enabling energy-efficient neural network acceleration. Simulation results demonstrate that the proposed ternary full adder and multiplier designs reduce overall energy consumption by 98% on average compared to existing ternary counterparts. Furthermore, implementing a 1-D neural network for efficient stress classification, the proposed design achieves a 99% reduction in energy-delay-product (EDP). The results indicate that the proposed architecture is well-suited for power constrained wearable devices in PCG-based stress detection applications.
Fields of Study & Subjects
Advanced Memory and Neural Computing
Low-power high-performance VLSI design
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- IEEE Transactions on Emerging Topics in Computing
- Volume
- 14
- Issue
- 2
- Pages
- 414–425
- Publication date
- 4 March 2026
- Language
- EN