A 22-nm 4.92 TOPS/W End-to-End RNS DNN Accelerator for Edge-AI Devices

This work presents an end-to-end Residue Numbering System (RNS) Deep Neural Network (DNN) accelerator targeting edge-AI devices. The proposed architecture translates the intrinsic advantages of RNS-particularly the efficient implementation of multiply-add operations-into system-level power efficiency gains. This is made possible by the introduction of novel architectural features, such as the amortization of high-complexity RNS operations (base extension, activation, and scaling), and the integration of bespoke RNS low-power techniques, such as a clock-gating scheme that exploits the periodic usage of the high-complexity RNS units, and voltage scaling that exploits the RNS capability to achieve clock frequency constraints with smaller supply voltages. Tradeoffs between hardware performance metrics of RNS implementations for various operational scenarios and RNS bases have been systematically analyzed, and comparisons against a conventional positional binary implementation have been conducted, guiding the optimal selection of design space parameters. Silicon power measurements on the 22-nm FDSOI prototype chips underpin the theoretical analysis and simulation results, which show considerable benefits of RNS-based DNN processing. These prove that RNS can increase the maximum achievable frequency of arithmetic circuits and result in 1.34× more energy-efficient processing compared to conventional binary counterparts. Compared to the state-of-the-art RNS-based DNN accelerator, the proposed architecture is 9× more power efficient, reaching a peak power efficiency of 4.92 TOPS/W.