Two-Stage Current Limiting Method for Fault Ride-Through Enhancement of Virtual Synchronous Generator

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Authors: Wei Tian, Linhai Zhang, Dongren Dai, Junkun Zhang, Yihang Zhang, Bo Li, Wentao Yang, Fei Lan, J Li
Cited by: 1

Abstract

By emulating inertia and damping, the virtual synchronous generator (VSG) enhances the dynamic support of grid frequency and voltage. However, under low-voltage faults, it is prone to severe overcurrent, power oscillations, and overload risks. To address these issues, a novel two-stage current limiting (TSCL) method is proposed in this article, which applies different limiting modes during the fault occurrence and recovery stages. Based on this, the combined effects of the active and reactive power control loops on the synchronization process under current limitation are thoroughly analyzed, and the absolute stability region (ASR) and the marginal stability region (MSR) are defined. Additionally, a transient control strategy based on power-angle characteristics is proposed to shorten synchronization time and suppress reactive power fluctuations. Finally, experimental results verify the effectiveness of the proposed method. Compared with conventional current-limiting approaches, the proposed scheme significantly reduces power oscillations and overload during fault recovery without increasing synchronization time, while maintaining strong synchronization capability.

Fields of Study & Subjects

Power Systems Fault Detection Islanding Detection in Power Systems HVDC Systems and Fault Protection

Publication details

Journal / source
IEEE Transactions on Industrial Electronics
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Pages
1–14
Publication date
1 January 2026