Low-Parasitic-Inductance Module With Interleaved Vertical PCB Layout for Dynamic Testing of SiC MOSFET Bare Die

Dynamic characterization of silicon carbide (SiC) MOSFET bare dies is essential but challenging due to their inherently fast switching speed, which makes them highly susceptible to parasitic inductance. To address this, this paper proposes a dynamic test module with ultra-low parasitic inductance. The design employs multiple short probes in parallel, reducing probe inductance below 2 nH and overall socket inductance to approximately 5.75 nH. An interleaved vertical PCB layout is implemented to minimize the power loop inductance through magnetic field cancellation, achieving an experimental value as low as 3.45 nH. This work first analyzes the detrimental effects of parasitic inductance to justify its minimization, then details the module design and probe characterization. A data-driven optimization method for the PCB layout is introduced. Experimental results validate the effectiveness of the proposed design.