A 28-GHz Compact Phased-Array Beamformer With 21.3-dBm P SAT and 5.2-dB Noise Figure in 40-nm CMOS

This article presents a 28-GHz compact high-power phased-array beamformer implemented in 40-nm CMOS. A parallel-combining transformer (PCT)-embedded transmitting/receiving (T/R) switch, cointegrated with a high-power power amplifier (PA) and a low-noise amplifier (LNA), is proposed to minimize insertion loss while enabling power combining. A bidirectional variable gain phase shifter (Bi-VGPS) is introduced to achieve amplitude and phase control in both TX and RX mode, facilitating a compact beamformer implementation. In addition, a frequency-selective suppression technique (FSST) is incorporated into the interstage matching network to generate a transmission zero, which enhances out-of-band (OOB) signal suppression. The beamformer demonstrates the measured peak gains of 22 dB (TX) and 24 dB (RX). The measured peak$P_{\mathrm {sat}}$/$P_{\mathrm {1{\,}dB}}$reaches 21.3/19.8dBm, and the corresponding PAEmax/PAE${}_{P1 \text {dB}}$is 18.3%/15.9%. A minimum noise figure (NF) of 5.2 dB is achieved in the RX mode. The TX and RX modes both support a phase resolution of 5.625° with$P_{\mathrm {out, avg}}$of 15.9 dBm and PAEavgof 8.3% at EVMrmsof −24.9 dB. The four-element phased-array beamformer occupies a compact chip area of only 3.6 mm2including pads.