CMOS Power Amplifiers With Dual-Power-Mode and Continuous-Power-Mode Operation for Wideband Back-Off Efficiency Enhancement

This article presents two CMOS power amplifiers (PAs) that support dual-power-mode (DPM) and continuous-power-mode (CPM) operations to enhance the efficiency under power back-off (PBO). In a DPM PA, a reconfigurable eight-way slotline-based series–parallel combiner (SSPC) provides high-power mode (HPM) and low-power mode (LPM). In a CPM PA, an adaptive bias network (ABN) is employed to enable continuous load modulation with input power. The DPM PA achieves 18–19.3-dBm saturated output power ($P_{\mathrm {sat}}$) and 20.4%–28.0% peak power-added efficiency (PAEmax) across 45–70 GHz in HPM, with 12.5%–17.1% PAE in LPM. The CPM PA delivers$P_{\mathrm {sat}}$of 17.7–19.0 dBm and PAEmaxof 17.0%–25.3% over 45–70 GHz and provides up to a 6.1%-point absolute improvement in the 6-dB PBO PAE over the HPM mode while maintaining comparable linearity. At 60 GHz, 64-QAM and 256-QAM measurements without digital predistortion show rms error vector magnitudes (EVMs) better than −25 dB. These results demonstrate that the proposed PA architecture provides wideband back-off efficiency improvement for high peak-to-average-power-ratio (PAPR) mm-wave transmitters.