A Compact D-Band Power Amplifier Using an Enhanced Slow Wave Structure With 16.2-dBm Output Power and 16.4% Peak PAE

This article presents a fully integrated D-band power amplifier (PA) with high output power and high efficiency, utilizing a two-way power combining technique and implemented in 28-nm bulk CMOS. An enhanced slow wave coplanar waveguide (ES-CPW) proposed in this article can achieve a higher phase constant and lower attenuation constant compared to conventional slow wave coplanar waveguides (S-CPWs), enabling simultaneous device miniaturization and performance enhancement. Based on this structure, a power combiner (PC) is designed to reduce the insertion loss while enhancing performance and minimizing the chip area, which achieves a 0.25-dB insertion loss with broadband operation and compact size. The PA measured results show a 3-dB bandwidth of 18.3 GHz from 122.3 to 140.6GHz. In addition, this PA can achieve a peak gain of 18.5dB, 16.2-dBm saturated output power (Psat), and a peak power-added efficiency (PAE) of 16.4% at 130 GHz. This allows the PA to achieve an average output power of 9.1 (6.5) dBm under 64-QAM (256QAM) modulation with a data rate of 45 Gb/s. To the best of the authors’ knowledge, the proposed PA realized the highest PAE, the widest power bandwidth (1-dB bandwidth), and the maximum data rate in CMOS technology and a similar operating band. Meanwhile, the total chip area is$0.32\times 0.31$mm2.