A Fully Differential D-Band Low-Noise Receiver With High-Efficiency Dielectric Resonator and Asymmetric Transformer in 40-nm CMOS

This article presents a high-gain, low-noise I/Q receiver operating at the D band, implemented using a 40-nm bulk CMOS process. To achieve high integration and low noise of the system, a high-efficiency dielectric resonator (DR) slot-line antenna is employed. The use of DR suppresses the surface wave leakage in the silicon substrate, minimizing the undesired coupling and ensuring stable radiation after integration with the receiver circuits. To enhance gain performance, the low-noise amplifier (LNA) incorporates the differential asymmetric transformer, which increases the effective transconductance ($G_{\text {m}}$) of the transistor while preserving the wideband characteristics of the common-gate (CG) topology. By leveraging the virtual ground of the differential structure, the$g_{\text {m}}$-boosting technique bypasses the parasitic impedance of decoupling capacitors and bonding wires, thereby achieving the superior performance and interference immunity compared with single-ended topology. The receiver employs a differential architecture and achieves simultaneous noise and impedance matching through an asymmetric transformer in conjunction with the co-design of the antenna. Measurement results demonstrate that the receiver achieves a peak gain of 39.9 dB with a low power consumption of 48.1 mW. The receiver circuit noise figure (NF) is 6.5 dB, while the overall system NF is 7.5 dB. To the best of the authors’ knowledge, this represents the lowest system NF for D-band receivers using a bulk CMOS process.