400-GHz Concurrent Transceiver Pixels for Short Range FMCW Radar Imaging

A 400-GHz concurrent transceiver imaging pixel with co-optimized output power, locking range (LR), and receiver noise performance is reported. The pixel integrates TX, RX, injection locking circuitry, and patch antenna within a ($\lambda $/2)2area, which makes the pixel more easily scalable to form focal plane arrays. The transceiver pixel is fabricated in the GF 22-nm FDSOI CMOS process with a chip area of$740\times 520$$\mu $m and achieves a measured peak effective isotropic radiated power (EIRP) of −14.8 dBm, a measured minimum DSB NF of 33dB, and an LR of 8.5 GHz while consuming only 63.2 mW of DC power at 0.8-V VDD. The operation of the pixel with an FMCW injection signal is demonstrated over 8.4 GHz at a ramp rate of 174 MHz/$\mu $s. Using a module assembled with a PCB, including a pixel IC and a 6-cm-diameter Cassegrain reflector, radar imaging of a pair of corner reflectors at 1.85 and 2 m away with a cardboard cover is demonstrated. These design and characterization efforts were used to establish a design framework/flow for concurrent transceiver pixels.