RAPID : R e-Configurable A dder Tree Based P erformance- I ncentivized AI D igital CIM Macro

Rapidly rising AI applications have driven the need for energy-efficient, high-throughput SRAM-embedded Compute-in-Memory (CIM) macros. This article proposes RAPID-CIM, a reconfigurable digital CIM featuring an M8T bit cell and an area-efficient hierarchical adder tree, which addresses performance limitations in state-of-the-art (SoTA) designs. The proposed architecture achieves a maximum 16.7× improvement in energy efficiency and an 8.6× increase in compute density compared to SoTA designs at CMOS 65nm. RAPID-CIMachieves superior performance for diverse AI workloads with scalable bit precision and sparsity-aware operations, reducing up to 3.2× operation cycles and a 30% memory bank usage and application accuracy within 97.85% Quality of Results (QoR). Thus, the proposed solution is a well-versed optimisation for resource constrained Edge-AI platforms.