Sensor Pixel Design for Nanosecond-Scale, Charge-Integrating CMOS Sensors

Charge-integrating CMOS sensors are an impactful solution for ultrafast, nanosecond-scale imaging in optical and X-ray detection applications where single-photon counting is not possible. Significant development effort has generated devices with minimum integration times approaching 1 ns and 1 ns inter-frame time for burst-mode sequences. In this regime, photodiode design can be a crucial factor in temporal response due to the extended signal current from the sensor to the readout circuit. This work explores photodiode pixel layout strategies that improve charge collection speed without requiring changes to the fabrication process or device operation. TCAD simulation of baseline and alternative designs is presented to demonstrate the device physics underlying the proposed changes. Finally, pulsed laser measurements on fabricated devices using the varied pixel layouts are shown. It is demonstrated that larger sensing electrodes are preferable to minimize charge collection time.