Temperature and Supply Voltage Dependence of Flip-Flop SE Cross-Sections at 7-, 5-, and 3-nm Bulk FinFET Nodes

Modern integrated circuits (ICs) are expected to operate reliably across a broad range of temperatures and supply voltages. This study examines the single-event upset (SEU) cross-section of D flip-flops (D-FFs) fabricated in 7-, 5-, and 3-nm bulk FinFET technology nodes under alpha particle irradiations. At the 3-nm node, the SEU cross-section decreases with increasing temperature, while at 5- and 7-nm nodes, it increases with increasing temperature. Lowering the supply voltage enhances the temperature’s impact. For the 3-nm node, comparisons between radiation-hardened and unhardened FF designs reveal different sensitivities to operating conditions.